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Run-time reconfigurable multiprocessors / Madhura Purnaprajna. 2010
Content
Introduction
Contributions
Organisation
Architecture
Architectural Models
Architectural Flexibility
Classifying Customisations
Cost of Flexibility
Architectural Design Space Exploration
Classifying Architectural Explorations
Ranking Architectural Merits
Multi-core Architectures
Commercial Multi-core Processors
Limitations of Existing Multi-core architectures
Initiatives for Customisable Multi-core Processors
The Concept: Run-time Reconfigurable Multiprocessors
Reconfiguration Mechanism
Advantages of the New Reconfiguration Mechanism
Summary
Application
Programmability
Methods of Application Description
Application Description for Parallel Processors
Managing Communication and Synchronisation
Drawbacks of Existing Methods
Architecture-Independent Application Characteristics
Model for Computation
Model for Synchronisation
Model for Communication
Comparing Application-specific Attributes
DSP Applications
Multiplier used in Elliptic Curve Cryptography
Self-organising Maps
Priorities: Computation, Communication, or Synchronisation
Restating Amdahl's Law
Speedup: Comparison to Amdahl's Law
Power: Comparison to Amdahl's Law
Impact on Energy
Summary
Application to Architectural Mapping
Applications and Architectures: Fixed vs. Alterable
Fixed Applications, Fixed Architecture
Alterable Applications, Fixed Architecture
Fixed Application, Alterable Architectures
Alterable Applications, Alterable Architecture
Application Mapping: Objectives and Methods
Compilation Flow
FPGA Flow
Comparing the two Design Flows
Merging Compilation and Synthesis Design Flows
Considerations for Merging Spatial and Temporal Design Flows
Optimisation Objectives
Cost Function
Adaptive Mapping in Reconfigurable Multiprocessors
Reconfiguration for Application Mapping
Advantages of the Multi-dimensional Mapping Approach
Summary
QuadroCore: Architecture
Reconfiguration Design Space
Instruction to Control Reconfiguration
Synchronisation
Communication
MIMD and SIMD operation
Word-length Configurability
Additional Instructions for Co-operative Multiprocessing
Compilation Flow
Time and Power Characteristics
Timing Characteristics
QuadroCore Power Distribution
Time and Power variations in the Reconfiguration Design Space
Instruction-level Power Model
Instruction Life Cycle
Memory Accesses
Register Accesses
ALU Accesses
Multiprocessor Synchronisation
Instruction Set Characterisation
Impact of Compilation Techniques
Implementation and Performance Measurements
Standard Cell Implementation
Post-layout Implementation Reports
FPGA Reports
Summary
QuadroCore: Applications
Design Flow for Resource Efficiency
Applications Mapped to QuadroCore
Timing Advantage of Reconfiguration
DSP Algorithms
Multiplier used in Elliptic Curve Cryptography
Self-organising Maps
Comparison: Parallelism, Speedup, Energy
Comparable Architectures
Extending the QuadroCore Multiprocessor
Platform for Validating Parallel Programs
Environment for Run-time Processor Customisation
Summary
Conclusions and Future Work
Summary
Future Work
Glossary
List of Figures
List of Tables
References
Author's Publications
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