Inhalt

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   List of Figures
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   List of Tables
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  Introduction
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   Motivation and Challenges
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   Aim of the Thesis
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   Contribution of the Thesis
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   Organization of the Work
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  Communication Framework for Embedded Systems
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  Framework
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   Tasks & Media
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   System Composition
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   Hardware & Software Interfaces
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   Modeling Interfaces
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   Scenarios for Interface Adaptation
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  System Architecture
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   The IFS System Architecture Model
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   Modeling the IFB Target-Platform
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   Hardware Execution Platform
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   Software Execution Platform
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   The Hardware/Software Interface
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   The Role of Reconfiguration
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   Summary
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  Background & Related Work
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   System-Level Design
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   Levels of Abstraction
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   Y-Chart and P-Chart
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   Intellectual Property and IP-Based Design
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   Interface-Aware (System-Level) Design Flows
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   Interface and IP Descriptions
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   Design Flows
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   Reconfigurable Systems
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   The FPGA -- A Reconfigurable Hardware Platform
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   Communication in Reconfigurable Architectures
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   How to Avoid the Communication Gap?
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   Dedicated Interface Synthesis Approaches
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   Interface Synthesis for Communication APIs (SW/SW)
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   Systematic Protocol Construction Approaches (HW/HW)
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   Protocol Wrapping/Adaptation Approaches (HW/HW)
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   Adaptation of Hardware Software Interfaces (HW/SW)
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   Summary
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   Interface Synthesis Requirements Specification
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  Interface Synthesis Methodology
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   Interface Synthesis Design Flow
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   Modeling Phase
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   Synthesis Phase
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   Integration Phase
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   IFS Modeling Concept
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   The Interface Synthesis Format
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   Interaction of XML and Java
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   UML2.0 and its Interaction with XML and Java
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  Concepts of the Interface Block
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   IFB Macro-Structure
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   IFB Reconfiguration
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   The Runtime Reconfigurable IFB (RTR-IFB)
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   Formalization of the FPGA-Placement
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   Runtime Self-Reconfiguration Using the RCU
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   Example: A Multi-Controller Design
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   Fail-Safe Behavior
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   Basic Concepts of Error Processing
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   Integrating Error Processing into an IFB
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   Case-Study: Robot Scenario
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   Relation to the ISO/OSI Model
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   Prototyping of Real-Time Communication
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   Summary
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  The Detailed Interface Synthesis Design Flow
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   Modeling-Phase
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   Modeling the UML2.0 Profile
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   Tool Coupling of the IFS-Editor with the CASE tool Fujaba
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   Model Transformation from UML2.0 to Java
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   Synthesis Phase -- Design Step1: IFB Model Synthesis
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   Prepare Synthesis Input
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   Basic Blocks
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   Protocol Matrix and Protocol Packages
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   Protocol Frames
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   Protocol Synthesis -- Generation of the Protocol State Machines
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   IFD-Mapping
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   IFD Optimization and Creation of the Protocol Frames
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   Assembly of the IFB Model (Intermediate Representation)
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   Synthesis Phase -- Design Step2: IFB Code Generation
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   Frame Processing
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   Adapted Frame Processing Model
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   Overview of the Generated VHDL Code Pattern
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   The Three levels of IFS Code Generation
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   Code Integration Phase
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   Extension of the Interface Synthesis Design Flow
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   Creation of a Globally Optimized Communication Infrastructure
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   Summary
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  The Interface Block (IFB)
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  IFB Hardware Template
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   Protocol Handler
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   Sequence Handler
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   Control Unit
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   Cycle Accurate Analysis of an IFB
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  Timing Analysis
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   Feasibility Analysis
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   Schedulability Analysis
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   IFB Optimization
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   Data Flow (Latency) Optimization
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   Area Optimization
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   Summary
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  Results
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   The IFS Design Environment: IFS-Editor
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   Case-Study: Adaptation of RFID to I2C
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   Comparison With Other Approaches
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  Conclusion and Outlook
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   Conclusion
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   Outlook
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  Extensions to the Interface Synthesis
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   Communication Cycles
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   Generating Basic Blocks
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   Grammar of the IFD-Mapping Language
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   VHDL Examples for the Created IFB Target Code
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   Template of the Reconfiguration Control Unit
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   Validity Period of Control Signals inside Protocol Frames
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   Own Previous Work
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   Advised Bachelor Thesis and Diploma Thesis
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   Bibliography
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   List of Abbreviations