In several domains, domain specific applications are developed with focus primarily on throughput. In addition to software and compiler optimization, it is necessary to optimize the processors. These optimizations can have different aims such as speed, power consumption, parallelism, real-time suitability, cost reduction, etc.This thesis contributes to support developers in the design of processors. The developed toolchain for this purpose contains the visual domain-specific language ViCE-UPSLA for the description of processors. The visual language is characterized by the usage of typical and established terms and symbols from the processor design and architecture domain. From the processor specification, the toolchain of ViCE-UPSLA generates cycle accurate simulators for interlocked or non-interlocked microarchitectures automatically.The other contribution of this thesis is the validation of the drafts. For this purpose, the dynamic and static validation methods are developed along the fault model and integrated in the toolchain. The dynamic validation methods are based on the approach of model based testing. With integrated generators, test cases are generated automatically from the processor's specification. By means of an additional specification language, the developers of processors are capable to understand or edit the test case specification.The specifications for ARM and CoreVA processors were developed, to prove the fitness of ViCE-UPSLA for design, simulation and validation of processors specifications. For the evaluation, simulators from different specifications are generated and the simulation is compared with selected applications.