Enabling reconfigurable hardware acceleration for ROS-based robotics applications / by Christian Lienen ; [Supervisors: Prof. Dr. Marco Platzner, Reviewers: Prof. Dr. Marco Platzner, Prof. Dr. Erdal Kayacan, Oral examination committee: Prof. Dr. Marco Platzner, Prof. Dr.-Ing. Roman Dumitrescu, Prof. Dr. Erdal Kayacan, Prof. Dr. Stefan Sauer, Dr. Tobias Kenter]. Paderborn, 2024
Inhalt
- Acknowledgments
- Abstract
- Zusammenfassung
- Publications
- Contents
- List of Figures
- List of Tables
- Listings
- Acronyms
- 1 Introduction
- 2 Background and Related Work
- 2.1 ReconOS: Operating System for Reconfigurable Computing
- 2.2 The Robot Operating System
- 2.3 Related Approaches for ROS-FPGA Integration
- 3 Design and Implementation of ReconROS
- 3.1 Design Considerations
- 3.2 ReconROS Architecture
- 3.3 ReconROS Design Flow
- 3.4 Programming Model
- 3.5 Experimental Evaluation
- 3.6 Chapter Conclusion
- 4 Task Mapping and Parallelism in ReconROS
- 4.1 Static Task Mapping
- 4.2 Dynamic Task Mapping
- 4.3 Exploitation of Parallelism
- 4.4 Experimental Evaluation
- 4.5 Chapter Conclusion
- 5 Communication Optimization in ReconROS
- 5.1 ReconROS Shared-Memory Communication
- 5.2 Intra-FPGA Communication Architecture
- 5.3 Gateways for Hardware-Mapped Topics
- 5.4 Communication Mapping Methodology
- 5.5 Evaluation
- 5.6 Chapter Conclusion
- 6 ReconROS Case Studies
- 7 Conclusion and Future Work
- Bibliography
- Colophon