An OpenCL- and HLS-based benchmark suite for reconfigurable hardware in HPC: performance evaluation and application / Marius Meyer. Paderborn, 2024
Content
- Acknowledgements
- Abstract
- Zusammenfassung
- List of Figures
- List of Tables
- Table of Contents
- Introduction
- FPGAs in HPC Systems
- Structure of FPGA PCIe Accelerator Boards
- HLS Toolchains and Their Opportunities for FPGAs
- Multi-FPGA Systems and inter-FPGA Networks
- FPGA Network Stacks and Communication Frameworks
- Benchmarking Single FPGAs
- HPCC Challenge for FPGAs
- Evaluation of Single FPGA Benchmarks
- Capturing Device Characteristics using Single-FPGA Benchmarks
- Chapter Conclusion
- Multi-FPGA Benchmarking and inter-FPGA Communication
- Definition and Implementation of Multi-FPGA Benchmarks
- Benchmark Execution and Evaluation
- Chapter Conclusion
- Case Study: Shallow Water Simulation
- Synthetic Benchmarking of ACCL Communication Approaches
- Acceleration of Shallow Water Simulation using ACCL
- Chapter Conclusion
- Related Work
- FPGA Benchmarks for HLS toolchains and Multi-FPGA systems
- LU Decomposition on FPGAs
- Multi-FPGA Applications
- Conclusion
- Glossary
- Appendices