Inhalt

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   Introduction
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   Contributions
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   Organisation
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   Architecture
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   Architectural Models
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  Architectural Flexibility
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   Classifying Customisations
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   Cost of Flexibility
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  Architectural Design Space Exploration
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   Classifying Architectural Explorations
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   Ranking Architectural Merits
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   Multi-core Architectures
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   Commercial Multi-core Processors
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   Limitations of Existing Multi-core architectures
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   Initiatives for Customisable Multi-core Processors
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   The Concept: Run-time Reconfigurable Multiprocessors
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   Reconfiguration Mechanism
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   Advantages of the New Reconfiguration Mechanism
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   Summary
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   Application
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   Programmability
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   Methods of Application Description
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   Application Description for Parallel Processors
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   Managing Communication and Synchronisation
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   Drawbacks of Existing Methods
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   Architecture-Independent Application Characteristics
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   Model for Computation
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   Model for Synchronisation
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   Model for Communication
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   Comparing Application-specific Attributes
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   DSP Applications
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   Multiplier used in Elliptic Curve Cryptography
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   Self-organising Maps
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   Priorities: Computation, Communication, or Synchronisation
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   Restating Amdahl's Law
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   Speedup: Comparison to Amdahl's Law
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   Power: Comparison to Amdahl's Law
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   Impact on Energy
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   Summary
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   Application to Architectural Mapping
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   Applications and Architectures: Fixed vs. Alterable
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   Fixed Applications, Fixed Architecture
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   Alterable Applications, Fixed Architecture
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   Fixed Application, Alterable Architectures
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   Alterable Applications, Alterable Architecture
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  Application Mapping: Objectives and Methods
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   Compilation Flow
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   FPGA Flow
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   Comparing the two Design Flows
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   Merging Compilation and Synthesis Design Flows
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   Considerations for Merging Spatial and Temporal Design Flows
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   Optimisation Objectives
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   Cost Function
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   Adaptive Mapping in Reconfigurable Multiprocessors
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   Reconfiguration for Application Mapping
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   Advantages of the Multi-dimensional Mapping Approach
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   Summary
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   QuadroCore: Architecture
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   Reconfiguration Design Space
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   Instruction to Control Reconfiguration
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   Synchronisation
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   Communication
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   MIMD and SIMD operation
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   Word-length Configurability
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   Additional Instructions for Co-operative Multiprocessing
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   Compilation Flow
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   Time and Power Characteristics
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   Timing Characteristics
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   QuadroCore Power Distribution
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   Time and Power variations in the Reconfiguration Design Space
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   Instruction-level Power Model
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   Instruction Life Cycle
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   Memory Accesses
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   Register Accesses
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   ALU Accesses
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   Multiprocessor Synchronisation
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   Instruction Set Characterisation
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   Impact of Compilation Techniques
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   Implementation and Performance Measurements
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   Standard Cell Implementation
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   Post-layout Implementation Reports
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   FPGA Reports
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   Summary
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   QuadroCore: Applications
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   Design Flow for Resource Efficiency
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   Applications Mapped to QuadroCore
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   Timing Advantage of Reconfiguration
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   DSP Algorithms
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   Multiplier used in Elliptic Curve Cryptography
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   Self-organising Maps
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   Comparison: Parallelism, Speedup, Energy
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   Comparable Architectures
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  Extending the QuadroCore Multiprocessor
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   Platform for Validating Parallel Programs
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   Environment for Run-time Processor Customisation
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   Summary
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   Conclusions and Future Work
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   Summary
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   Future Work
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   Glossary
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   List of Figures
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   List of Tables
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   References
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   Author's Publications