Content

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   Abstract
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   Zusammenfassung
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   Contents
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   List of Tables
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   List of Listings
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   List of Figures
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  Introduction
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   Motivation
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   Contributions of this Thesis
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   Thesis Structure
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  Computing Concepts, Trends and Domains
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   Compute Devices: Basic Terms and Concepts
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   Target Metrics
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   Instruction-Programmable Processors
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   Computing in Circuits
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   Field-Programmable Gate Arrays
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  Trends in Technology, Architectures and Devices
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   Scaling in Process Technology: Continuity and Changes
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   Impact on Processor Architecture
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   Accelerators
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   FPGA Accelerators
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  Computing domains and markets
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   General-Purpose and Special-Purpose Computing
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   Complex Embedded Systems in Automotive
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   Modern Smartphones
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   FPGAs in Special-Purpose Computing and Beyond
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   Markets and Workloads of General-Purpose Computing
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   Personal and Mobile Computers
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   Sever Class Computers
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   Opportunity Matrix
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   Chapter Conclusion
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  The Case for general-purpose adoption of FPGAs with the help of Overlay-Architectures
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  Between Performance and Productivity Walls
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   Productivity of General-Purpose Architectures
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   Impact of System Architectures
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   FPGA Productivity
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   Three Pillars for General-Purpose FPGAs
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  FPGA Overlays
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   Instruction-Programmable Overlays
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   Reconfigurable Hardware beyond FPGAs
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   Structurally Programmable Overlays
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   Chapter Conclusion
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   Stereo-Matching Kernels on Overlay and Custom Designs
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   Introduction to the Stereo-Matching Problem
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   Stereo-Matching Algorithm with Inherent Parallelism
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   Cost Initialization
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   Cost Aggregation
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   Scanline Optimization
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   Disparity Refinement
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   Software Implementation
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  Utilized FPGA Platforms and Programming Models
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   Maxeler Platform and Programming Paradigm
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   Convey HC-1 Platform with Vector Processor Overlay
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   Comparison of FPGA Platforms
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   Kernel-Centric Acceleration
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   Kernel-Designs for two FPGA platforms
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   Aggregation Kernels
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   Scanline Kernels
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   Synthesis and Integration
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   Kernel Summary
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   Experimental Setup
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   Evaluated Systems
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   Input Data
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  Evaluation and Comparisons
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   Stereo-Matching System Performance
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   Platform Overheads
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   Kernel Performance
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   Quantifying Overlay Overheads through Hardware-Normalization
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   Overheads by Kernel Groups
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   Estimates on Design Efforts
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   Limitations of the Comparison
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   Related Work
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   Chapter Conclusion
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   Compilation and Runtime Techniques for FPGA Accelerators
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   Motivation
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  Approach
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   Toolflow for Heterogeneous Executables
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   Code Extraction
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   Vectorization
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   Runtime Decisions
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   Experimental Setup
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   Evaluation
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   Comparison to Hand-Written Kernels of Chapter 4
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   Further Experiments
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   Related Work
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   Excursion to Offloading Decisions at Runtime
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   System-Level Scheduling and Task Migration
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   Chapter Conclusion
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  CPU-accelerator System Integration
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   Motivation
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   Proposed Architecture
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   Relation to Existing Architectures
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  Method and Framework
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   Estimation Model
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   Partitioning Approach
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   Design Space Exploration
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   Speedups per benchmark
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   Memory integration
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   Accelerator Size
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   Execution Efficiency
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   Interface Latency
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   Related Work
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   Chapter Conclusion
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  Conclusion
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   Summary
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  Outlook
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   Towards a Library of Overlay Architectures and Tools
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   And Beyond
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   Acronyms
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   Author's publications
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   Bibliography