TY  - CHAP
AU  - Rammig, Franz Josef
DP  - Universität Paderborn
LA  - eng
PY  - 2009
SP  - 259-276
T3  - VHDL for simulation, synthesis and formal proofs of hardware
TI  - Approaching system level design
UR  - https://nbn-resolving.org/urn:nbn:de:hbz:466:2-3265
Y2  - 2026-01-21T04:36:28
ER  -