The operation of digital CMOS circuits in the subthreshold region, i.e. at supply voltage levels below the transistors threshold voltage, offers a niche for applications where minimizing the energy or power consumption is the most important design criterion whereas performance requirements are moderate and of secondary importance. Typically, the energy consumption of a circuit can be reduced by one, the power consumption by four or more orders of magnitude during subthreshold operation. The design of subthreshold circuits must, however, gives rise to a number of challenges, as the influence of process, voltage, and temperature variation is much more pronounced compared to conventional supply voltages. This thesis studies the design of integrated digital circuits aiming at a resource efficient and robust operation in the subthreshold region. In a first step, two standard cell libraries optimized for subthreshold operation in process technologies with feature sizes of 90 nm and 65 nm are presented as a basis for the implementation of arbitrary digital systems. Based on these subthreshold standard cells, two prototypical ASIC implementations are presented, demonstrating the benefits of subthreshold operation. The first circuit fabricated in the 90 nm process consists of four 32 bit ALUs. The second ASIC fabricated in the 65 nm process contains two instances of an entire subthreshold processor based on a 32 bit architecture with a six-stage pipeline as well as subthreshold SRAM blocks. A novel system providing adaptive voltage and frequency control under the influence of process and operating parameter variation is utilized. This ASIC may serve as a basic element for energy efficient embedded systems.