The continuous downscaling of feature sizes in modern process technologies allows to integrate increasingly complex functionality onto a decreasing chip area. While this enables to build highly advanced applications, the risk of producing marginal hardware is increasing as well. Marginal hardware does not result in faulty behavior at the beginning of the product lifecycle, but can degenerate into an actual defect quickly [...]. It has been shown that some marginalities influence the affected element by increasing its switching delay by a small amount. Therefore, they can be modeled as a small delay fault. These faults can be detected by using Faster-than-At-Speed Test (FAST), which overclocks the circuit under test [...]. FAST alone, however, is not sufficient to deal with the challenges that modern process technologies pose to testing. In this work, a concept for a built-in FAST is presented, which integrates all required test infrastructures onto the chip itself. This allows for instance to periodically re-test the device, such that changes in the timing behavior can be observed, that can hint to an early life failure. Two challenges for built-in FAST are addressed and solved in the work at hand. Firstly, the number of required test frequencies for FAST is minimized. Secondly, a method is presented to generate constraints for a synthesis tool, such that the tool generates specialized scan-chains for FAST. These, in combination with a simple masking system, allow to reduce unwanted side effects of FAST and support X-tolerant compaction. Extensive simulations show [...], that built-in FAST can indeed be realized with a lower cost than one would expect.